DC reset analog memory with negative feedback
K. Harada, T. Kawano · IEEE Transactions on Magnetics · 1967
Previously proposed analog memory devices of the second harmonic type have two defects: that resetting the memory cores by ac demagnetization requires considerable time, and that the input-output characteristic of the memory device is nonlinear. This paper discusses a device in which these defects are overcome. Two cores are used in which the zero memory state corresponds to saturation magnetization states of the cores. Consequently, quick reset to the zero state is possible. The output voltage has both fundamental and second harmonic components of the ac bias used for readout. Linearity is improved by negative feedback. The rectified and filtered output of the 2-core circuit is fed back and compared with the memory write-in signal. The error signal is used to set the memory.