On designing robust testable CMOS combinational circuits
B. Gupta, Yashwant K. Malaiya, Y. Min, Rochit Rajsuman · IEE Proceedings E Computers and Digital Techniques · 1989
The potential invalidation of two-pattern tests for detecting stuck-open faults in CMOS combinational circuits has been studied from a functional point of view. Two methods of testable realisations avoiding the problem are presented. A new type of two-level testable realisation is proposed in which both stuck-open and stuck-short faults can be detected. In both the methods, valid test patterns are applied at the inputs and the logic responses are observed at the output. Finally, multilevel realisations of combinational functions have been considered in which all stuck-short faults are three-pattern testable and all stuck-open faults are two-pattern testable.