Don't Care discovery for FPGA configuration compression
Zhiyuan Li, Scott Hauck · 1999
One of the major overheads in reconfigurable computing is the time it takes to reconfigure the devices in the system. The configuration compression algorithm presented in our previous work [1] is one efficient technique for reducing this overhead. In this paper, we develop an algorithm for finding Don’t Care bits in configurations to improve the compatibility of the configuration data. With the help of the Don’t Cares, higher configuration compression ratios can be achieved by using our modified configuration compression algorithm. This achieves a compression ratio of a factor of 7, where our previous algorithm only achieved a factor of 4. 1. Configuration Compression FPGAs are often used as powerful hardware for applications that require high speed computation. One major benefit provided by FPGAs is the ability to reconfigure during execution. For systems in which reconfiguration was done infrequently, the time to reconfigure the FPGA was of little concern. However, as more and more applications involve run-time reconfiguration, fast reconfiguration of FPGAs becomes an important issue [2]. In most systems an FPGA must sit idle while it is being reconfigured, wasting cycles that could otherwise be used to perform useful work. For example, applications on the DISC and DISC II system spend 25 % [3] to 71 % [4] of their execution time performing reconfiguration. Thus, a