Flexible systolic design with asynchronous communication protocols for discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT)
Kamran Reihani, Wiley E. Thompson, Yiping Fan · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1994
In this paper, a spiral systolic array (SA) architecture with asynchronous controls for the real time realization of an N point DFT and IDFT is considered. The study includes the overall system block diagram, propagation of data between array PEs, operations within each PE, and the PE protocol for computing an N point DFT. The idea is to design self-timed processors and communication protocols to gain control of data streams such that each computation can start if all its data are available, thus reducing waste time. The PE protocol controls input data flow properly and efficiently. The proposed SA has large throughput at the expense of more hardware than FFTs.