Analysis of Noise Margins Due to Device Parameter Variations in Sub-100nm CMOS Technology
Zhicheng Liang, Makoto Ikeda, Kunihiro Asada · 2007
Increasing level of process variation in the sub-100 nm silicon technology is becoming an important issue. In this paper we describe an approach to estimate the impact of process variations on the static CMOS and the dual-rail PLA down to 32 nm process. This approach is built on accurate variation modeling, published data including the ITRS, Predictive Technology Models, and Monte-Carlo analysis. The analysis results show that a challenge due to insufficient noise margins is posed to the static CMOS at 32 nm, and to the dual-rail PLA from 90 nm. Then a one-side virtual ground structure is also proposed to improve the noise margins of the dual-rail PLA. The improved dual-rail PLA is shown to work down to 32 nm process with keeping an operational margin of 150 mv.