Reliability enhancement of bi-stable PUFs in 65nm bulk CMOS
Mudit Bhargava, Cagla Cakir, Ken Mai · 2012
We demonstrate the efficacy and associated costs of three reliability enhancing techniques for bi-stable PUF designs (SRAM and sense amplifier-based) - directed accelerated aging, multiple evaluations, and activation control. Measured results from a 65nm bulk CMOS full custom PUF testchip demonstrate that these technique are able to reduce the percentage of unreliable bits by up to 40%, 83%, and 71% respectively.