7.1 A low-power 64Gb MLC NAND-flash memory in 15nm CMOS technology
Mario Sako, Yoshihisa Watanabe, Takao Nakajima, Jumpei Sato, Muraoka Kazuyoshi, M. Fujiu, Fumihiro Kouno, M. Nakagawa, Masami MASUDA, Koji Kato, Terada Yuri, Yuki Shimizu, Mitsuaki Honma, Akihiro Imamoto, Tomoko Araya, Hayato Konno, Takuya Okanaga, Tomofumi Fujimura, Xiaoqing Wang, Mai Muramoto · 2015
The demand for high-throughput NAND Flash memory systems for mobile applications such as smart phones, tablets, and laptop PCs with solid-state drives (SSDs) has been growing recently. To obtain higher throughput, systems employ multiple NAND Flash memories operating simultaneously in parallel. The available power for a mobile device is severely restricted and the peak total operating current may be high enough to cause large supply-voltage drop or even an unexpected system shutdown. Therefore it is important for NAND Flash memories to reduce operating power and peak operating current.