A unique non-intrusive approach to non-ATE Based cul-de-sac SoC debug
Vasant Easwaran, Virendra Bansal, Greg Shurtz, Rahul Gulati, Mihir Mody, Prashant Karandikar, Prithvi Shankar · 2014
Rapid increasing complexity of chips due to integration of multiple processing elements along with a rich set of peripherals for connectivity needs, poses new set of debug challenges on silicon. The spectrum of issues ranges from minor functional bugs, random timing related bugs to dead on-arrival (DoA) chip. The prior methods of doing silicon test were using ATE (Automatic Test Equipment's) and using trace data under software control, bringing its own set of limitations. This paper proposes a new method to overcome the above limitations by introducing internal state observations at the boundary of chip that can be viewed by probing these pins. The proposed method consists of routing hardware observability signal from every individual IP to pins, which are controlled by means of boot-pins on the chip. The solution accomplishes the same with no additional overhead in terms of pin count and helps to debug DoA silicon. This method is implemented in a multicore SoC (System-on-chip) catering to the automotive market. The actual result from SoC usage has shown to save up to 83% effort in debugging actual issues on silicon by adding about 0.2% more cost in terms of silicon area.