Self-characterization of Combinatorial Circuit Delays in FPGAs
Justin S. J. Wong, Pete Sedcole, Peter Y. K. Cheung · 2007
This paper proposes a built-in self-test (BIST) method to measure accurately the combinatorial circuit delays on an FPGA. The flexibility of the on-chip clock generation capability found in modern FPGAs is employed to step through a range of frequencies until timing failure in the combinatorial circuit is detected. In this way, the delay of any combinatorial circuit can be determined with a timing resolution of 1 ps or lower. A parallel implementation of the method for self-characterization of the delay of all the LUTs on an FPGA is also proposed. The method was applied to an Altera Cyclone-II FPGA (EP2C35). A complete self-characterization was achieved in 3 seconds, utilizing only 13 kbit of block RAM to store the results. This self-characterization method paves the way for matching timing requirements in designs to FPGAs as a means of combating the problem of process variations.