Hardware/software formal co-verification using hardware verification techniques
Minh Duc Nguyen, Wolfgang Kunz · 2012
This paper describes a methodology for hardware/software formal co-verification. In the proposed methodology, a unified computational model is constructed for a hardware/software system under verification, in which the software and the hardware are tightly connected. In addition, we proposed a systematic method to formulate properties for the system using extracted information from software programs. Consequently, the properties can describe system behaviors in both software and hardware level. The interval property checking (IPC) technique is used to verify the computational model against the properties. We applied the proposed methodology to verify an industrial LIN being ported to an open source micro controller.