SoC Level Verification Using System Verilog
Purvi D. Mulani · 2009
The SoC level verification of AMBA AHB interconnect matrix and I2C DUT is presented in this paper. The verification environment has been developed and test cases have been implemented for I2C DUT. The assertions and monitor are developed to check the functionality of Interconnect matrix of multilayer AHB Lite. The whole verification is done using SystemVerilog hardware description and verification language. The verification environment developed is reusable.