A Study of Layout Strategies for Lowering RF CMOS Device Tolerances
Troels Kolding · 1999
Although tolerance levels for CMOS devices at gigahertz frequencies constitute a major challenge to RF-IC designers, little has been published about this subject. This paper presents a large number of measurements on various devices; including capacitors, inductors, and MOSFETs. The devices have been fabricated in four different standard submicron CMOS technologies. The reliability issues of on-wafer measurements are covered and a link to robust test fixture design is made. To establish a methodology for reducing tolerances of RF CMOS devices, various component layout techniques are studied. Advanced configurations such as fractal capacitors, shielded multi-level inductors, and multi-fingered transistors have been attempted. Besides from enhancing the component performance, many of these techniques are useful for lowering device spread as well.