H.264 video parallel decoder on a 24-core processor
Shikai Zhu, Yu Zheng, Shile Cui, Zhiyi Yu, Xiaoyang Zeng · 2013
This paper presents an implementation of H.264 decoder on a 24-core processor. H.264 provides many new features that require complex computations compared to the previous video coding standards, thus introduces great challenges to implement it efficiently. Multiprocessor emerges as a good solution because it provides high parallelism rather than high clock frequency to improve the system performance energy efficiently. By utilizing hardware accelerators and different levels of parallelism mechanism including function-level parallelism, data-level parallelism and thread-level parallelism, our proposed H.264 decoder shows a throughput of 58fps@720p at 800MHz with 780mW power dissipation.