An Automatic Test-Generation System for Large Digital Circuits
Shigehiro Funatsu, Masato Kawai · IEEE Design & Test of Computers · 1985
A new test-generation system (FUTURE) for large digital circuits (more than 10K gates) is based on a nine-valued FAN algorithm. Fault simulation adopts a concurrent simulation adopts a concurrent simulation technique. The system consists of four major modules: fault modeling, random pattern generation, algorithmic pattern generation, and fault simulation. The system can be a powerful CAD tool and effectively generate test patterns for large sequential circuits with Scan Path.