A new IEEE 1149.1 boundary scan design for the detection of delay defects
Sungju Park, Tae-Hyung Kim · 2000
Delay defects on I/O pads, interconnections of a board, or interconnections among embedded cores can not be tested with the current IEEE 1149.1 boundary scan design.This paper introduces a simple design technique which slightly modifies the TAP controller to test delay defects by postponing the UpdateDR with EXTEST instruction.Furthermore 2log(N+2) interconnect test patterns are proposed for both static and delay testing.