Efficient parallel time-slot interchanger for high-performanceSDH/SONET digital crossconnect systems
H. Obara · Electronics Letters · 2001
A parallel design of time-slot interchangers is refined in order to scale the interchangers' capacity in an efficient manner. Performance analysis shows that this design scheme requires significantly less memory compared with a conventional parallel design because of newly implemented load-balancing switches, while keeping its switching control complexity to a minimum.