A 32-bit CMOS microprocessor with on-chip cache and TLB
Hideki Kadota, Jiro Miyake, Ichizo Okabayashi, Takehiko Maeda, Tadashi OKAMOTO, M. Nakajima, K. Kagawa · IEEE Journal of Solid-State Circuits · 1987
A 32-b general-purpose microprocessor has been developed using 1-/spl mu/m CMOS technology. The chip, containing 372 K transistors, operates at a 80-ns machine cycle time with a 5-V power supply. For virtual and hierarchical memory system support, a 64-entry full-associative translation lookaside buffer (TLB) and a 2-kbyte instruction cache are implemented on the chip. The internal access times for the TLB and cache are 22 and 18 ns, respectively. The microarchitecture has been designed to reduce the pipeline to three stages, simplifying the control path and obtaining high-speed performance. The data path of this chip is also enhanced with hardware, such as a barrel shifter and multiplier/divider. The chip performance has been measured to be 5.1 million instructions per second (MIPS) and 50-ns-access main memory.