Designing in scaled technologies: 32 nm and beyond
Stephen V. Kosonocky, Thomas D. Burd, Keith Kasprak, Rich Schultz, R. Stephany · 2012
VLSI technology scaling in the 32-nm node and beyond has presented designers with increasing challenges to obtain performance gains, power and area reductions each successive generation. Maximum voltage limits, decreasing interconnect performance, and device changes have forced designers to rethink system and circuit design for enhanced system performance and improved user experience.