An energy-aware heuristic constructive mapping algorithm for Network on Chip
Yancang Chen, Lunguo Xie, Jinwen Li · 2009
Network on Chip (NoC) is a promising interconnection solution for the ever-increasing systems complexity and design productivity gap. Mapping the IP cores onto a given platform is an important phase of NoC design which can greatly affect the performance and energy consumption of the chip. In this paper, we analyze the preexistent mapping algorithms, and categorize them into three classes according to the tracks of obtaining the near-optimal mapping. We present a fast hybrid heuristic constructive algorithm, i.e. CMAP, to map cores onto NoC architectures with the goal of minimizing the total communication energy consumption. The algorithm is applied to two real applications and a series of task graphs generated by TGFF package. The accuracy, efficiency and scalability of the proposed algorithm are confirmed by comparing the results of our algorithm with other mapping algorithms1.