Achieving extreme scan compression for SoC Designs
Peter Wohl, John A. Waicukauski, Jonathon E. Colburn, Milind Sonawane · 2014
High volume testing of complex System on Chip (SoC) designs at reasonable test cost requires high test data and test time compression. We present a multilevel scan compression architecture that combines a flexible test compression core with an efficient dynamic broadcast structure and a high speed data access technique. Full X-tolerance, power-aware scan shift and diagnosis are supported through the entire architecture. We present a flow for assembling the various components that limits the impact on area and timing by minimizing test signals and improving modularity of the inserted design-for-test (DFT) structures. These techniques provided a reduction of 600x in test data volume and over 2300x in test time on large Graphics Processor Units (GPU) designs.