A High-performance Multi-level NAND Flash Memory with 43nm-node Floating-gate Technology
Munetaka Noguchi, Toshitake Yaegashi, Hiroshi Koyama, Mutsuo Morikado, Y. Ishibashi, Sadato Ishibashi, Kazumi Ino, Ken Sawamura, T. Aoi, Tooru Maruyama, Akihiro Kajita, Eiji Ito, M. Kishida, Kazushige Kanda, Koji Hosono, S. Miyamoto, Fuminori Ito, Y. Hirata, Gertjan Hemink, Masaaki Higashitani · 2007
Multi-level programming is demonstrated with 43 nm-node NAND floating-gate megabit cells for the first time, by thinning an inter-gate dielectric film to less than 13 nm. 43 nm-node cobalt-silicide control-gate and copper bit-line technologies are developed to achieve low resistances of the word lines and bit lines.