Hardware reduction for compositional microprogram control unit dedicated for CPLD systems
А. А. Баркалов, Larysa Titarenko, Łukasz Smoliński · 2013
The method of hardware reduction is proposed which is dedicated for compositional microprogram control unit implemented in CPLD. The method is based on using more than one data source in calculation of microinstruction address. Such approach permits to the decrease the number of logic blocks used for the implementation of the controller in the target CPLD. The paper presents the conditions needed to apply the method. An example of the proposed method application is given.