Balanced high-speed residue number VLSI multiplier with error detection
Hao‐Yung Lo, Ted C. Yang · IEE Proceedings G Circuits Devices and Systems · 1991
A balanced residue number VLSI multiplier is proposed which eliminates the extra delay for an unbalanced residue multiplier. The number of adding stages used in the VLSI multiplier is reduced from three to two. The paper also describes how redundant residue number system (RNS) properties can be used for an error detection. These improvements allow a residue multiplier with a 48–72 bit dynamic range, to perform 3.3 M multiplication/s without pipelining or 10 M multiplication/s with pipelining.