High Speed Generic Network Interface for Network on Chip Using Ping Pong Buffers
K. Swaminathan, Lakshminarayanan Gopalakrishnan, Seok‐Bum Ko · 2012
Connecting different Intellectual Property (IP) cores with Network on Chip (NoC) router using Network Interface (NI) is a challenging task due to its asynchronous nature and data width. In this paper, a generic high-speed Network Interface for Network on Chip using Ping Pong Buffers is proposed in order to ensure the seamless high throughput between the router and processing core. The proposed scheme uses simple control logic to handle the read and write operations simultaneously in the memory modules. This proposed method is analyzed with the existing Asynchronous First in First Out (FIFO) based NIs with different encoding schemes like One-Hot encoding and Johnson encoding. The optimal depth of the asynchronous FIFOs is calculated based on router frequency, processing element frequency, packet size and flit size at router and processing element using Practical Extraction and Report Language (PERL) and the required Register Transfer Level (RTL) Verilog Hardware Description Language (HDL) and timing constrain is created by Perl scripting itself. The NI is implemented using the asynchronous FIFOs and ping pong - double buffering scheme using Altera Stratix III FPGA. The synthesis results show that the proposed architecture enhances the speed of NI by 30 % when memory depth is 8 and enhances speed by 11% when memory depth is 256.