Horus: Large-Scale Symmetric Multiprocessing for Opteron Systems
Ram Mohan Chowdary Kota, Richard Oehler · IEEE Micro · 2005
Horus lets server vendors design up to 32-way Opteron systems. Horus is the only chip that targets the Opteron in an SMP implementation. By implementing a local directory structure to filter unnecessary probes and by offering 64 Mbytes of remote data cache, the chip significantly reduces overall system traffic as well as the latency for a coherent hypertransport transaction.