Super Digit-Serial Systolic Multiplier over GF(2^m)
Chiou‐Yng Lee · 2012
This paper presents a new super digit-serial systolic multiplier architecture for computing multiplication over GF(2m). The proposed architecture has low latency and total computation time and is thus suitable for high-performance implementations of the cryptographic schemes such as the elliptic curve cryptography (ECC). Through comparisons, we show the efficiency improvements of the proposed architectures compared to the previously-presented ones. The presented architectures for multiplication and exponentiation based on systolic structures make hardware implementations of the cryptographic systems more efficient and high-performance.