A Parallel Stereo Matching Algorithm Core for FPGA Modeled by DSP Builder
Xiang Zhang, Zhang Wei Chen · Applied Mechanics and Materials · 2014
This paper proposes a FPGA implementation to apply a stereo matching algorithm based on a kind of sparse census transform in a FPGA chip which can provide a high-definition dense disparity map in real-time. The parallel stereo matching algorithm core involves census transform, cost calculation and cost aggregation modules. The circuits of the algorithm core are modeled by the Matlab/Simulink-based tool box: DSP Builder. The system can process many different sizes of stereo pair images through a configuration interface. The maximum horizon resolution of stereo images is 2048.