Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow
Igor Loi, Federico Angiolini, Luca Benini · 2007
Three-dimensional (3D) manufacturing technologies are viewed as promising solutions to the bandwidth bottlenecks in VLSI communication. At the architectural level, Networks-on-chip (NoCs) have been proposed to address the complexity of interconnecting an ever-growing number of cores, memories and pe