Optimised bit serial modular multiplier for implementationon field programmable gate arrays
William Peter Marnane · Electronics Letters · 1998
A high-speed architecture for bit serial modular multiplication is presented. The design of this array is highly regular, allowing the specific logic and routing resources available in field programmable gate arrays (FPGAs) to be exploited. Furthermore, an optimised array is presented which exploits the re-programmability of the FPGA, such that a longer bit length can be implemented on the same FPGA.