A test port for interfacing and debugging ARM9 processors implemented in FPGA
Ken Bryan F. Fabay, John Cris F. Jardin, Kervin John C. . Jocson, Bernard Raymond D. Pelayo, Anastacia B. Alvarez, Joy Alinda R. Madamba, Louis P. Alarcón · 2012
This paper presents an FPGA implementation of a test port for interfacing and debugging ARM9 processors. The system included a communication interface for debugging the processor, together with the JTAG-based module that granted debugging capability to the selected ARM9 core. Also included was an application software debugger that readily shows the comparison of expected and gathered results from the processor core. The debugging system for the selected ARM9 processor was successfully implemented in a Virtex 5 FPGA development board and was tested using the supported data processing instructions. The latency measured was 0.3 ms per instruction for a baud rate of 4800.