Hardware efficient scheme for generating error vector to enhance the performance of secure channel code
Celine Mary Stuart, P. P. Deepthi · 2015
Security, reliability and hardware complexity are the main issues to be addressed in resource constrained devices such as wireless sensor networks (WSNs). Secure channel coding schemes have been developed in literature to reduce the overall processing cost while providing security and reliability. The security of a channel coding scheme against various attacks is mainly decided by the nature of intentional error vectors added to the encoded data. The methods available in literature to generate random error vectors increase the encoding complexity for each message block. Also the error vectors generated are not able to provide much security. A novel method is proposed in this paper to generate intentional error vector with sufficient weight, so that the security of the secure channel code is increased by a large margin without causing any additional encoding complexity. Results show that the proposed model is effective in incorporating security in resource constrained sensor networks.