A 151-mm$^{2}$ 64-Gb 2 Bit/Cell NAND Flash Memory in 24-nm CMOS Technology
Koichi Fukuda, Yoshihisa Watanabe, Eiichi Makino, Koichi Kawakami, Jumpei Sato, Teruo Takagiwa, Naoaki Kanagawa, Hitoshi Shiga, Naoya Tokiwa, Yoshihiko Shindo, Takeshi Ogawa, Edahiro Toshiaki, Makoto Iwai, Osamu Nagao, Junji Musha, Takatoshi Minamoto, Yuka Furuta, Kosuke Yanagidaira, Yuya Suzuki, Dai Nakamura · IEEE Journal of Solid-State Circuits · 2011
A 64-Gb MLC (2 bit/cell) NAND flash memory with the highest memory density to date as an MLC flash memory, has been successfully developed. To decrease the chip size, 2-physical-plane configuration with 16 KB wordline-length, a new bit-line hook-up architecture, and a top-metal-congestion-free optimized peripheral circuit floor plan, are introduced. As a result, 151 mm2die size with an excellent 79% cell area efficiency is achieved. Newly introduced precharge detect algorithm and smart precharge algorithm improve program throughput by 10%. 14 MB/s program throughput is obtained, which is comparable or even higher performance than NAND flash memories reported in the previous 30 nm technology generation. The proposed smart precharge algorithm reduces program operation current by 6%, and 25 mA operation current with 16 KB programming is achieved. Moreover, a high-speed asynchronous DDR interface is incorporated and 266 MB/s data transfer is achieved.