Performance study of virtual-channel router for Network-on-Chip
Feiyang Liu, Huaxi Gu, Yintang Yang · 2010
Network-on-Chip (NoC) overcomes the main constraints of traditional bus-based System-on-Chip (SoC). It introduces the principle of interconnection network into SoC design. Router is the main component of NoC and determines performance to a large extend. Virtual-channel router is one of the promising router architectures for Network-on-Chip, for its low delay and high network throughput. In this paper, we evaluate the performance of virtual-channel router with different buffer schemes. Various simulations are carried out and the analysis of the simulation results help to achieve a better configuration for virtual-channel router, considering network performance and buffer requirement.