A pipelined 32b NMOS microprocessor
Christopher Rowen, S. Przbylski, Norman Paul Jouppi, Thomas R. Gross, John D. Shott, John LeRoy Hennessy · 1984
THIS REPORT will cover a 32b microprocessor(MIPS) which combines a small streamlined instruction set with NMOS implementation to create a CPU of modest size, low power dissipation and high regularity.