A 0.5-W 64-kilobyte snoopy cache memory with pseudo two-port operation
Tsukasa Kobayashi, K. Nogami, Tsukasa Shirotori, Y. Fujimoto, Y. Biwaki, H. Nohara, M. Kobayashi, Kiyoshi Kobayashi, K. Sawada · IEEE Journal of Solid-State Circuits · 1991
A 64-kbyte snoopy cache memory was developed. The modified double word-line architecture with word-line buffers resulted in a large-size memory and a time-multiplex snoop operation by the pseudo-two-port method with a single-port cell. The flexible expandability was achieved by cascading multiple cache memories. The device was successfully implemented with 1.0- mu m double-polysilicon and double-metal CMOS technology. Low-power sense amplifiers and comparators limited power dissipation to 0.5 W at 40 MHz.>