Static test compaction for IDDQ testing of bridging faults in sequential circuits
Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu, Kozo Kinoshita · Systems and Computers in Japan · 2000
This paper presents a static test compaction method for IDDQ testing of sequential circuits. Test compaction reduces test application time and tester memory and consequently reduces testing cost. Particularly for IDDQ testing, measurement of IDDQ is time-consuming, and thus test compaction is a very important issue. In the proposed method, test subsequences are removed and replaced with shorter subsequences by considering state transition of a circuit under test, so that original fault coverage is guaranteed. The effectiveness of the proposed method is demonstrated by experimental results for ISCAS'89 benchmark circuits. © 2000 Scripta Technica, Syst Comp Jpn, 31(11): 41–50, 2000