Configuration memory size reduction of a Dynamically Reconfigurable Processor based on a register-transfer-level packet data transfer scheme
Yoshichika Fujioka, Michitaka Kameyama · 2012
A register-transfer-level packet routing scheme is proposed to reduce a configuration memory size of a Dynamically Reconfigurable Processor (DRP). The RT(Register-Transfer)-driven concept makes the configuration memory size very small, because packets are not required to be provided at all the clock cycles. Buffer-less routers can be used to construct a compact DRP, if offline scheduling/allocation is effectively utilized to avoid packet collision. Dynamic reconfiguration of Local Memories (LMs) is also realized by the packet data transfer control. It is evaluated that the packet-routing configuration memory size can be reduced to about 1/10 under the Functional Unit (FU) utilization ratio of 10% in comparison with the conventional DRP.