A 300 MHz embedded flash memory with pipeline architecture and offset-free sense amplifiers for dual-core automotive microcontrollers
Shinya Kajiyama, Masamichi Fujito, Hideo Kasai, Makoto Mizuno, T. Yamaguchi, Yutaka Shinagawa · 2008
We propose a novel 300 MHz embedded flash memory for dual-core microcontrollers targeting shared ROM architecture. One of the features is a three-stage pipeline read operation, which enables reduced access pitch and therefore reduced performance penalty due to shared ROM access conflict. The second feature is a highly sensitive sense amplifier that achieves efficient pipeline operation with two-cycle latency one-cycle pitch because of a shortened sense time of 0.63 ns. The combination of the pipeline architecture and the proposed sense amplifiers achieves significant reduction in access-conflict penalties with shared ROM and enhanced performance of 32-bit RISC dual-core microcontrollers by 30%.