A 10Gbps HEC HUNT circuit for ATM over SDH/SONET
Ciaran Toal · 2004
This paper presents the design and study of various header error check (HEC) HUNT architectures for ATM frame delineation and explores the trade-offs between the data-path (parallelism) and the hardware cost. An 8-bit, 16-bit, 32-bit and a 64-bit HEC HUNT circuit has been implemented and analysed in terms of hardware cost, speed, and data throughput rate. It is possible, with the 64-bit data-path architecture, to achieve data rates beyond 10 Gbit/s on the latest FPGA technology. Post layout synthesis results are presented for the new Altera Stratix 2 FPGA technology.