Testing cross-talk induced delay faults in static CMOS circuit through dynamic timing analysis
Bipul Chandra Paul, Kaushik Roy · 2003
In deep submicron (DSM) circuits the critical path obtained from static timing analysis may often be incorrect due to the significant effect of crosstalk. In this paper we present a new algorithm based on timed automatic test pattern generation (ATPG) to generate a list of critical paths of a circuit and the corresponding input vectors to sensitize these paths under cross-talk. The algorithm based on modified PODEM handles multiple aggressors to a victim node and properly activates the aggressors to obtain maximum coupling to the victim. Several circuits were tested using this algorithm and results were verified by HSPICE simulation.