Area-time efficient diminished-1 multiplier forFermat number transform
A.S. Ashur, M.K. Ibrahim, A. Aggoun · Electronics Letters · 1994
A new regular implementation of a diminished-1 multiplier is presented which requires less silicon area and achieves higher speed than existing designs. For a multiplier where the modulus involved is F4, a 34% increase in the speed of operation is achieved in comparison to that of Sunder et al.