A fault-tolerant and hierarchical routing algorithm for NoC architectures
Mojtaba Valinataj, Pasi Liljeberg, Juha Plosila · 2011
This paper presents a routing method that increases the reliability and product yield of Network-on-Chip (NoC) architectures while incurs a negligible cost. This method has a multi-level fault-tolerance capability and therefore it is capable to tolerate more faulty links and routers with extra cost in higher levels. The proposed algorithm uses dynamic reconfiguration to handle permanent faults but after each configuration it selects new deterministic paths to route the packets. Thus, this algorithm is the reconfigurable extension of deterministic methods. In addition, it is a turn-based routing method and does not need any virtual channel (VC). The effectiveness of the proposed method is evaluated through analysis and simulations. We analytically show that the reliability of a NoC is enhanced by different levels of this method. The experimental results show that the area overhead is only 2.8% for a state of the art router including 64-bit flits and 4-flit input buffers.