Multi-clock path analysis using propositional satisfiability
Kazuhiro Nakamura, Shinji Maruoka, Shinji Kimura, Katsumasa Watanabe · 2000
Abstract — We present a satisfiability based multi-clock path analysis method. The method uses propositional satisfiability (SAT) in the detection of multi-clock paths. We show a method to reduce the multi-clock path detection problems to SAT problems. We also show heuristics on the conversion from multi-level circuits into CNF formulae. We have applied our method to IS-CAS89 benchmarks and other sample circuits. Experimental results show the improvement on the manipulatable size of circuits by using SAT. I.