Analysis of FPGA-based AES round architectures
David Bermingham · 2005
This paper explores the power, delay and area efficiency of AES round architectures when implemented on field-programmable gate arrays (FPGAs). Modern FPGAs provide attractive solutions for cryptographic applications when compared to application specific integrated circuits (ASIC) design, reducing costs, allowing greater flexibility and can provide high throughput There has been a varied number of AES architectures proposed since 2001 for implementation on FPGAs. In this paper we implement three popular AES round architectures, allowing for analysis and comparison of the area/delay/power tradeoffs when mapped to Xilinx VirtexII-Pro FPGAs.