Scheme for designing concurrent checking and easily testable PLAs
D.L. Tao, Parag K. Lala, Carlos R. P. Hartmann · IEE Proceedings E Computers and Digital Techniques · 1990
The existing concurrent checking schemes for PLAs are based on the assumption that a single fault can occur during normal operation. However, in practice, after a PLA has been fabricated it may contain more than one fault. In certain cases such faults mask each other, e.g. a fault in the functional part of the self-checking PLA may be masked by a fault in the checker. Thus, after a self-checking PLA has been fabricated, it must be tested in the off-line mode to detect all single faults in both the functional part and checker(s), before it can be used in the concurrent checking mode. In the paper, we present a new technique for designing self-checking PLAs which are easily testable in the off-line test mode and execute concurrent checking during the normal operation. A design example shows that the overall performance of the proposed technique for large PLAs in terms of area overhead (including routing), delay, and fault-detection capability is better than any of the schemes currently available.