VHDL as a specification language for high-level synthesis system
Wojciech Sakowski, Miroslaw Ossysek, Benedykt Nowak · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1992
The paper presents the results of research work carried out as an introductory effort toward development of a high level synthesis system. The restrictions imposed on the behavioral specifications and the language extensions provided to control the synthesis process are discussed. The internal machine representation of the initial specification is presented.