A low power multimedia processor implementing dynamic voltage and frequency scaling technique
Tadayoshi Enomoto, Nobuaki Kobayashi · 2013
A DVFS controlled 90-nm CMOS multimedia processor was developed. To make full use of the advantages of DVFS, we developed the A2BC algorithm that can predict the optimum clock frequency and the optimum supply voltage. The measured power dissipation of the DVFS controlled multimedia processor was significantly reduced. Thus, DVFS employing the A2BC algorithm is one of the most useful power reduction for future video encoding applications.