TOWARDS THE DESIGN OF A HIGH PERFORMANCE ACTIVE NODE
Jean-Patrick Gelas, S. el Hadri, Laurent Lefèvre · Parallel Processing Letters · 2003
Achieving high performance in active networks is one of the most challenging task. In this paper, we propose an architecture for the design of next generation gigabit active routers . This original architecture allows service deployment of 4 levels: inside network cards, in kernel space, in user space and on distributed computing resources. We deploy and validate this architecture within the Tamanoir execution environment. First experiments on gigabit network platforms are described.