Hierarchical architecture for area-efficient integratedN-portmemories with latency-free multi-gigabit per second access bandwidth
Hans Jürgen Mattausch · Electronics Letters · 1999
A two-level hierarchy is exploited for an area-efficient integrated N-port memory architecture, based on 1-port memory cells. The architecture is applicable to all types of dynamic, static and nonvolatile memory. It allows simultaneous read/write access from all ports, with access-rejection probability adjustable to application needs.