PSLP: padded SLP automatic vectorization
Vasileios Porpodas, Alberto Magni, Timothy M. Jones · 2015
The need to increase performance and power efficiency in modern processors has led to a wide adoption of SIMD vec-tor units. All major vendors support vector instructions and the trend is pushing them to become wider and more power-ful. However, writing code that makes efficient use of these units is hard and leads to platform-specific implementations. Compiler-based automatic vectorization is one solution for this problem. In particular the Superword-Level Parallelism (SLP) vectorization algorithm is the primary way to auto-matically generate vector code starting from straight-line scalar code. SLP is implemented in all major compilers, in-cluding GCC and LLVM. SLP relies on finding sequences of isomorphic instruc-tions to pack together into vectors. However, this hinders the applicability of the algorithm as isomorphic code sequences are not common in practice. In this work we propose a solu-tion to overcome this limitation. We introduce Padded SLP (PSLP), a novel vectorization algorithm that can vectorize code containing non-isomorphic instruction sequences. It in-jects a near-minimal number of redundant instructions into the code to transform non-isomorphic sequences into iso-morphic ones. The padded instruction sequence can then be successfully vectorized. Our experiments show that PSLP improves vectorization coverage across a number of kernels and full benchmarks, decreasing execution time by up to 63%. 1.